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genlinx ? gs9002a serial digital encoder data sheet features device description the gs9002a is a monolithic bipolar integrated circuit designed to serialize smpte 125m and smpte 244m bit parallel digital signals as well as other 8 or 10 bit parallel formats. this device performs the functions of sync detection, parallel to serial conversion, data scrambling (using the x 9 + x 4 +1 algorithm), 10x parallel clock multiplication and conversion of nrz to nrzi serial data. it supports any of four selectable serial data rates from 100 mb/s to over 360 mb/s. the data rates are set by resistors and are selected by an on-board 2:4 decoder having two ttl level input address lines. other features such as a sync detector output, a sync detector disable input, and a lock detect output are also provided. the x 9 + x 4 + 1 scrambler and nrz to nrzi converter may be bypassed to allow the output of the parallel to serial converter to be directly routed to the output drivers. the gs9002a provides pseudo-ecl outputs for the serial data and serial clock as well as a single-ended pseudo-ecl output of the regenerated parallel clock. the gs9002a directly interfaces with cable drivers gs9007a, gs9008a and gs9009a. the device requires a single +5 volt or -5 volt supply and typically consumes 713 mw of power while driving 100 ? loads. the 44 pin plcc packaging assures a small footprint for the complete encoder function. ? fully compatible with smpte-259m serial digital standard supports up to four serial bit rates to 400 mb/s accepts 8 bit and 10 bit ttl and cmos compatible parallel data inputs x 9 + x 4 + 1 scrambler, nrzi converter and sync detector may be disabled for transparent data transmission pseudo-ecl serial data and clock outputs single +5 or -5 volt supply 713 mw typical power dissipation (including ecl pull-down loads). 44 pin plcc packaging pb-free and green applications 4? sc , 4:2:2 and 360 mb/s serial digital interfaces for video cameras, vtrs, signal generators ordering information revision date: june 2004 functional block diagram patent no.5,357,220 gennum corporation p.o. box 489, stn a, burlington, ontario, canada l7r 3y3 tel. (905) 632-2996 fax: (905) 632-5946 gennum japan: shinjuku green tower building 27f 6-14-1, nishi shinjuku shinjuku-ku, tokyo 160-0023 japan tel: +81 (03) 3349-5501 fax: +81 (03) 3349-5505 document no. 24149 - 1 sync detect disable gs9002a pld loop filter rvc00 rvc01 rvc02 rvc03 lock detect serial clock sync detect pclk in parallel data in (10 bits) p/s converter pclk out drs1 drs0 sync detect data rate switch regulator cap phase frequency detect charge pump vco input latch div by 10 generator 6 7-16 17 22 19 3 20 43 29 36 32 33 35 31 34 26 scrambler/ serializer select sclk lock detect nrz nrzi 2:1 mux serial clock 42 scrambler serial data serial data 39 38 not recommended for new designs
GS9002ACPM 44 pin plcc oc to 70c no GS9002ACPMe3 44 pin plcc oc to 70c yes
2 of 11 24149 - 1 not recommended for new designs parameter symbol conditions min typ max units notes supply voltage v s operating range 4.75 5.0 5.25 v power consumption p d sdo/sdo connected to (v cc -2v) thru 100y resistors, pck out - 690 870 mw connected to v ee via 1k ? same as above with sck/sck - 710 900 mw also connected to (v cc -2v) thru 100 ? resistors. supply current i s sdo/sdo connected to (v cc -2v) - 155 190 ma thru 100y resistors, pck out connected to v ee via 1k ? same as above with sck/sck to (v cc -2v) v thru 100 ? resistors. - 170 205 ma see figure 15 ttl inputs-high v ihmin t a = 25c 2.0 - - v ttl inputs-low v ilmax t a = 25c - - 0.8 v logic input current i inmax - 2.5 10 a ttl outputs-high v ohmin t a = 25c 2.4 - - v ttl outputs-low v olmax t a = 25c - - 0.5 v sync detect o/p i osync - - 4.0 ma sink & source serial outputs high v oh t a =25c, r l =100 ? to v cc -2v -0.875 - -0.7 v (sdo & sck) low v ol ( v cc -2v ) -1.8 - -1.5 v serial data outputs bit rates br sdo r l = 100 ? to 100 - 400 mb/s ( v cc -2 volts ) signal swing v sdo 700 850 1000 mv p-p rise/fall times t r , t f - 500 - ps 20% - 80% jitter t j(sdo) 143 mb/s - 400 - ps p-p see note 1 270 mb/s - 300 - ps p-p see fig. 16 serial clock outputs frequency ? sck r l = 100 ? to 100 - 400 mhz see fig. 12, 13 ( v cc -2 volts ) signal swing v sck - 800 - mv p-p see fig. 14 serial data to clock timing t d see figure 9 - 1.4 - ns data lags clock lock time t lock c loop filt = 0.1f - 1 1.2 ms r loop filt = 3.9k ? parallel clock output frequency ? pcko r l = 1k ? to v ee 10 - 40 mhz ? pcko = ? sck /10 signal swing v pcko - 800 - mv p-p rise/fall times t r , t f - 700 - ps 20% - 80% jitter t jpcko - 400 - ps p-p parallel data & clock inputs risetime t r t a = 25c 500 - - ps setup t su 3- -ns hold t hold 3- -ns note 1: measured using pck-in as trigger source on 1ghz analog oscilloscope. v cc = 5v, v ee = 0v, t a = 0c to 70c unless otherwise shown gs9002a - encoder dc electrical characteristics gs9002a - encoder ac electrical characteristics v cc = 5v, v ee = 0v, t a = 0c to 70c, v loop filter =2.6 v unless otherwise shown, t a = 25c with respect to v cc (sdo and sdo) (sck and sck) (pck out) parameter symbol conditions min typ max units notes
3 of 11 24149 - 1 not recommended for new designs absolute maximum ratings parameter value/units supply voltage 5.5 v input voltage range (any input) -v ee < v i < v cc dc input current (any one input) 10 ma power dissipation (v s = 5.25 v) 1 w operating temperature range 0 c t a 70 c storage temperature range -65 c t s 150 c lead temperature (soldering 10 seconds) 260 c fig. 1 gs9002a encoder pin connections sdo sdo v ee drs0 drs1 rvc00 rvc01 rvc02 rvc03 v ee c. reg sync det. dis. v cc1 v ee sync det. v cc3 v ee v ee sck sck v cc2 a v cc2 b v cc3 v ee nc v ee loop filt. v cc3 lock det. pck out v ee pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 pd9 pck in parallel data inputs vco frequency set resistors gs9002a top view 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 44 43 42 41 40 sss v ee
4 of 11 24149 - 1 not recommended for new designs the gs9002a encoder is a bipolar integrated circuit used to convert parallel data into a serial format according to the smpte 259m standard. the device encodes both eight and ten bit ttl-compatible parallel signals producing serial data rates up to 400 mb/s. it operates from a single five volt supply and is packaged in a 44 pin plcc. functional blocks within the device include the input latches, sync detector, parallel to serial converter, scrambler, nrz to nrz i converter, ecl output buffers for data and clock, pll for 10x parallel clock multiplication and lock detect. the parallel data (pd0-pd9) and parallel clock (pck-in) are applied via pins 7 through 17 respectively. sync detector the sync detector looks for the reserved words 000-003 and 3fc-3ff, in ten bit hex, or 00 and ff in eight bit hex, used in the trs-id sync word. when the occurrence of either all zeros or ones at inputs pd2-pd9 is detected, the lower two bits pd0 and pd1 are forced to zeros or ones, respectively. this makes the system compatible with eight or ten bit data. for non - smpte standard parallel data, a logic input, sync disable (6) is available to disable this feature. scrambler the scrambler is a linear feedback shift register used to pseudo-randomize the incoming serial data according to the fixed polynomial (x 9 +x 4 +1). this minimizes the dc component in the output serial data stream. the nrz to nrzi converter uses another polynomial (x+1) to convert a long sequence of ones to a series of transitions, minimizing polarity effects. gs9002a serial digital encoder - detailed device description phase locked loop the pll performs parallel clock multiplication and provides the timing signal for the serializer. it is composed of a phase/frequency detector, charge pump, vco and a divide-by-ten counter. the phase/frequency detector allows a wider capture range and faster lock time than that which can be achieved with a phase discriminator alone. the discrimination of frequency also eliminates harmonic locking. with this type of discriminator, the pll can be over-damped for good stability without sacrificing lock time. the charge pump delivers a 'charge packet' to the loop filter which is proportional to the system phase error. internal voltage clamps are used to constrain the loop filter voltage between approximately 1.8 and 3.4 volts. the vco, constructed from a current-controlled multivibrator, features operation in excess of 400 mb/s and a wide pull range ( 40% of centre frequency). vco centre frequency selection the wide vco pull range allows the pll to compensate for variations in device processing, temperature variations and changes in power supply voltage, without external adjustment. a single external resistor is used to set the vco current for each of four centre frequencies as selected by a two bit code through a 2:4 decoder. the current setting resistors are connected to the rvco0 through rvco3 inputs (34, 33, 32 and 31). the decoder inputs drs0 and drs1 (36, 35) are ttl compatible inputs and select the four resistors according to the following truth table. drs1 drs0 resistor selected 0 0 rvco0 (34) 0 1 rvco1 (33) 1 0 rvco2 (32) 1 1 rvco3 (31) a 2:1 multiplexer (mux) selects either the direct data from the p/s converter (serializer) or the nrzi data from the scrambler. this mux is controlled by the scrambler/serializer select (sss) input pin 26. when this input is low the mux selects the scrambler output. (this is the mode used for smpte 259m data). when this input is high the mux directly routes the serialized data to the output buffer with no scrambling or nrz to nrz i conversion. the lock detect circuit disables the serial data output when the loop is not locked by turning off the 2:1 mux. the lock detect output is available from pin 20 and is high when the loop is locked. the true and complement serial data, sdo and sdo are available from pins 38 and 39 while the true and complement serial clock, sck and sck are available from pins 43 and 42 respectively. if the serial clock is not used pins 43 and 42 can be connected to v cc . the regenerated parallel clock (pck out) is available at pin 19. this output is a single ended pseudo-ecl output requiring a pull down resistor. if regenerated parallel clock is not used pin 19 can be connected to v cc .
5 of 11 24149 - 1 not recommended for new designs gs9002a pin descriptions pin no. symbol type description 1 v ee power supply: most negative power supply connection. 2 v cc3 power supply: most positive power supply connection for the pll and scrambler. 3 sync det. o ttl output level that detects the occurrence of all zero?s or all one?s at inputs pd2-pd9 and pulses low for three pck-in durations. used to detect smpte 259m reserved words (000-003 and 3fc-3ff) in trs sync word. parallel data bits pd0 and pd1 are set low or high when pd2 - pd9 are low or high respectively. 4 v ee power supply: most negative power supply connection. 5v cc1 power supply: most positive power supply connection for the input data latches and serializer. 6 sync det. i ttl level input that disables the internal sync detector when high. this allows the disable gs9002 to serialize 8 or 10 bit non - smpte standard parallel data. 7-16 pd0-pd9 i ttl level inputs of the parallel data words. pd0 is the lsb and pd9 is the msb. 17 pck-in i ttl level input of the parallel clock. 18 v ee power supply: most negative power supply connection. 19 pck out o pseudo-ecl output representing the re-clocked parallel clock and is derived from the internal vco. the vco is divided by 10 in order to produce this output. 20 lock det. o ttl level output which goes high when the internal pll is locked. 21 v cc3 power supply: most positive power supply connection for the pll and scrambler. 22 loop filt. i connection for the r-c loop filter components. the loop filter sets the pll loop parameters. 23 v ee power supply: most negative power supply connection. 24 nc 25 v ee power supply: most negative power supply connection. 26 sss i scrambler/serializer select. ttl level input that selects scrambled nzri output when logic low or direct serializer output when logic high. 27 v ee power supply: most negative power supply connection. 28 v cc3 power supply: most positive power supply connection for the pll and scrambler. 29 c reg i compensation rc network for internal voltage regulator that requires decoupling with a series 0.1f capacitor and 820 ? resistor. components should be located as close as possible to the pin. 30 v ee power supply: most negative power supply connection. 31 r vco3 i vco resistor 3: analog current input used to set the centre frequency of the vco when the two data rate select bits (pins 35 and 36) are both set to logic 1. a resistor is connected from this pin to v ee . 32 r vco2 i vco resistor 2: analog current input used to set the centre frequency of the vco when the data rate select bit 0 (pin 36) is set to logic 0 and the data rate select bit 1 (pin 35) is set to logic 1. a resistor is connected from this pin to v ee . 33 r vco1 i vco resistor 1: analog current input used to set the centre frequency of the vco when the data rate select bit 0 (pin 36) is set to logic 1 and the data rate select bit 1 (pin 35) is set to logic 0. a resistor is connected from this pin to v ee . 34 r vco0 i vco resistor 0: analog current input used to set the centre frequency of the vco when the two data rate select bits (pins 35 and 36) are both set to logic 0. a resistor is connected from this pin to v ee . 35,36 drs0, 1 i ttl level inputs to the internal 2:4 demultiplexer used to select one of four vco frequency setting resistors (r vco0 - r vco3 ). (see above)
6 of 11 24149 - 1 not recommended for new designs gs9002a pin descriptions (continued) pin no symbol type description 37 v ee power supply: most negative power supply connection. 38,39 sdo/sdo o serial data outputs (true and inverse). pseudo-ecl differential outputs representing the serialized data. these outputs require 390 ? pull down resistors. 40 v cc2b power supply: most positive power supply connection for the serial data ecl output buffers. 41 v cc2a power supply: most positive power supply connection for the serial clock ecl output buffers. 42,43 sck/sck o serial clock outputs (inverse and true). pseudo-ecl differential outputs of the serial clock (10x parallel clock). these outputs require 390 ? pull-down resistors. 44 v ee power supply: most negative power supply connection. v ee 1k 1k v cc input v r1 v ee v cc sync det 5k input / output circuits fig. 2 pin no. 3 sync detect fig. 4 pin no. 19 parallel clock out fig. 5 pin no. 20 lock detect fig. 3 pins no. 6, 7 - 16, 17,26 sync disable, parallel data, parallel clock, scrambler/serializer select v ee pck out 1k v cc 1k v cc lock detect 10k v ee v cc
7 of 11 24149 - 1 not recommended for new designs v cc v ee drs1 drs0 v r1 fig. 6 pins no. 35, 36 data rate select v ee r vcox v select v cc 800 v r2 =2.15v i vco fig. 7 pins no. 31 - 34 frequency setting registors r vco0 -r vco3 fig. 9 waveforms 200 sdo sdo v cc v ee 200 fig. 8 pins no. 38, 39, 42, 43 serial outputs (data & clock) t su t hold t clkl = t clkh parallel clock plck 50% parallel data pdn t d serial data out (sd0) 50% serial clock out (sck) t d 50%
8 of 11 24149 - 1 not recommended for new designs 38 39 43 42 19 22 notes: resistors 1, 2, 3 and 4 are used to set the vco centre frequency. for 143/177 mb/s 6k ? , 270 mb/s 2.7k ? , 360 mb/s 1.8k ? all resistors in ohms, all capacitors in microfarads unless otherwise stated. represent test points. data +10 20 26 6 2,5,21,28,40,41 +5v 18,23 25,27 30,37 44 17 36 35 29 0.1 *150 34 33 32 31 1,4 1 2 3 4 10k data rate select dip switch (see truth table, fig. 2) 5k 100 100 6x100n 82 2n4400 +5v loop locked l.e.d. parallel clock out 330 data 0 data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 8 data 9 clock 3.9k 0.1 0.1 gs9002a pd0 pdi pd2 pd3 pd4 pd5 pd6 pd7 pd8 pd9 pck in drs0 drs1 creg rvco1 rvco2 rvco3 rvco4 vee lock sss sync (6x vcc) det. dis. sck pck-out loop filt 10k 4x0.1 820 common +5v 10k 1k 8 9 10 11 12 13 14 15 16 100 data clock clock 100 sdo sdo sck 7 +5v 1m *10p * this rc network is used to slow down fast pclk risetimes ( 500ps). it is not required if risetimes exceed 500ps. fig. 11 gs9002a test circuit fig. 10 timing diagram e a v s a v 4? sc data stream active video & h blanking t r s sync detect active video t r s t r s active video & h blanking 4:2:2 data stream pclk in pdn sync detect e a v s a v h blnk h blnk sync detect xxx 3ff 000 000 xxx xxx 3ff 000 000 xxx
9 of 11 24149 - 1 not recommended for new designs loop filter voltage (v) fig. 16 output jitter typical performance curves (v s = 5v, t a = 25 c unless otherwise shown) fig. 12 vco frequency fig. 13 vco frequency vs loop filter voltage 0 1 2 3 4 5 6 7 8 9 10 frequency setting resistance (ky) v loop =2.6v loop filter voltage (v) 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 optimal loop filter voltage 600 550 500 450 400 350 300 250 200 150 100 50 0 fig. 14 serial output level (data & clock) 0 10 20 30 40 50 60 70 v s = 5.25v v s = 5.0v 0 10 20 30 40 50 60 70 ambient temperature (c) fig. 15 supply current v s = 4.75v ambient temperature (c) v s = 4.75v v s = 5.0v v s = 5.25v 200 190 180 170 160 150 r vco = 1.8k r vco = 2.7k r vco = 6.3k 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 143 mb/s 270 mb/s 800 700 600 500 400 300 200 100 600 550 500 450 400 350 300 250 200 150 100 50 1000 950 900 850 800 750 700 jitter p-p (ps) vco frequency (mhz) frequency (mhz) current (ma) serial output (mv)
10 of 11 24149 - 1 not recommended for new designs data 0 data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 8 data 9 clock 6 3 38 39 43 42 19 22 8 notes: resistors 1, 2, 3 and 4 are used to set the vco centre frequency. see figures 12 and 13. all resistors in ohms, all capacitors in microfarads unless otherwise stated. represent test points. * these resistors are used to slow down fast input edges ( 500ps ) and prevent the input signals from ringing below the v ee rail. cable driver gs9007a this signal is 12db below actual sck level and is used for test purposes 0 0 0 0 1 1 1 0 2 1 1 3 out 1 out 1 out 2 out 2 20 26 6 2,5,21,28,40,41 sdo1 (75 ? ) ser. in ser . in vee 1k 3.9k +5v 18,23 25,27 30,37 44 17 36 35 29 0.1 820 34 33 32 31 1,4 0.1 100 1 2 3 4 10k 10pf data rate select dip switch (see truth table) 5k 390 390 7 4 1 6x100n 0.1 2n4400 +5v loop locked l.e.d. 4x150 1p8 68 parallel clock t.p. serial clock (50 ? ) 180 2 330 vcc 5 gs9002a pd0 pdi pd2 pd3 pd4 pd5 pd6 pd7 pd8 pd9 pck in drs0 drs1 creg rvco0 rvco1 rvco2 rvco3 vee lock sss sync (6x vcc) det. dis. sck sck pck-out loop filt 10k 4x0.1 10 + 10 + 47 0.1 18p 47 27 0.1 1.0 1.0 1.0 68 1p8 68 1p8 68 1p8 +5v sdo2 (75 ? ) sdo1 (75 ? ) sdo2 (75 ? ) data rate select truth table 10k drs1 drs0 rvco no. sdo sdo 7 8 9 10 11 12 13 14 15 16 1.0 +5v 1m * 100 100 100 100 100 100 100 100 100 100 100 100 100 fig. 17 genlinx ? serial digital chipset gs9002/7a application circuit
11 of 11 24149 - 1 not recommended for new designs caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation application circuit figure 17 shows a typical application circuit of the gs9002a driving a gs9007a cable driver. gennum corporation assumes no responsibility for the use of any circuits described herein and makes no representations that th ey are free from patent infringement. ? copyright march 1991 gennum corporation. all rights reserved. printed in canada. revision notes added lead-free and green information. for latest product information, visit www.gennum.com document identification product proposal this data has been compiled for market investigation purposes only, and does not constitute an offer for sale. advance information note this product is in development phase and specifications are subject to change without notice. gennum reserves the right to remove the product at any time. listing the product does not constitute an offer for sale. preliminary the product is in a preproduction phase and specifications are subject to change without notice. data sheet the product is in production. gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible.

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